1. Technical Field
This invention relates generally to integrated circuits, and more particularly to estimating the static power consumption of an integrated circuit.
2. Background Art
A static power consumption (also referred to as leakage) of an integrated circuit (IC) depends on the state of each cell of the IC. A cell may include any hierarchical level of IC components that are higher than a transistor, and may be represented as a netlist of gates. Full characterization of a cell regarding a static power consumption for a given voltage, temperature, and process-corner requires 2n constants, where n is the number of inputs of the cell.
Conventionally, the estimation of the static power consumption of a netlist of gates (a cell) can be performed at two levels: gate level, where a gate is modeled as a black-box, or transistor level, where the internal logic of a gate is required. A transistor level estimation, e.g., with a SPICE simulation, provides a high degree of accuracy. However, the required simulation time may be prohibitively long for large integrated circuits. Some approaches based on a simplified transistor level model for leakage estimation have been proposed. Nevertheless, those approaches are still relatively slow, and require a detailed analysis of the physical sources of leakage present in a gate.
The state of the art approaches for leakage modeling and estimation at the gate level can be classified into three groups: constant approaches, table-based approaches and Boolean-condition based approaches. A constant approach models the static consumption as a single constant equal to the mean value of the measured leakages of the cell. This model does not consider any input dependency, and thus is very imprecise. In addition, it cannot be used for input dependent static power optimization techniques such as pin reordering, input vector control, etc.
A table-based approach models the static power consumption of each input state independently. The accuracy of this approach is the highest possible at this level of abstraction. However, the leakage estimation is very complicated and resource consuming, since this approach requires calculating independently the probabilities of all possible input states.
A Boolean-condition based approach basically neglects the smaller terms in the static power table of the table-based approach. The static power consumption is measured and modeled only for some input states. In the technologies where sub-threshold leakages dominate gate leakage, there are a small number of states with relatively high leakages. As such, this technique may allow a reduction in the sizes of the estimation tables, and a reduction in the number of internal Boolean expressions required to be calculated. However, this technique can be very imprecise in modern technologies with higher gate-leakage, and may also be very slow.
Based on the above, there is a need in the art for a solution to estimate the static power consumption of an integrated circuit, which satisfies simultaneously the requirements of accuracy, efficiency, and flexibility.